/* global React */
// ─── Project: CORDIC FW and ASIC Implementation and Optimization ─────────────
// To edit: change any field below. Add/remove metrics rows as needed.
// cover options: "mod" | "scanlines" | "gf"
// ─────────────────────────────────────────────────────────────────────────────
window.PROJECT_cordic_implementation = {
  order: 4,
  slug: "cordic-fw-asic",
  name: "CORDIC FW and ASIC Implementation and Optimization",
  sub: "ARM Cortex-A7 firmware optimization and 15-stage pipelined ASIC implementation of vectoring-mode CORDIC.",
  year: "2026",
  stack: ["C", "VHDL", "ARM Cortex-A7", "NEON SIMD", "ASIC", "Vivado"],
  status: "verified · optimized",
  cover: "mod",

  // Image path relative to portfolio root
  image: null,

  // 4 metrics shown across the top of the project page
  metrics: [
    ["pipeline",     "15-stage CORDIC"],
    ["gate equiv.",  "5,280"],
    ["instructions", "259 → 82 · 68% reduction"],
    ["performance",  "6x fewer cycles vs. baseline"],
  ],

  // Links: [label, url]
  links: [
    ["PRIVATE REPO", "REQUEST_ACCESS"],
  ],

  problem:
    "Implemented and optimized a vectoring-mode CORDIC algorithm across both software and hardware targets, with the goal of improving execution efficiency on an ARM Cortex-A7 while also developing a high-throughput ASIC architecture with bit-exact agreement between software and RTL.",

  approach:
    "Developed the software reference in C for ARM Cortex-A7 and optimized the implementation using NEON SIMD, loop unrolling, and multi-issue instruction scheduling. In parallel, designed a 15-stage pipelined CORDIC datapath in VHDL for ASIC implementation. Verified the RTL in Vivado against the software reference to ensure bit-exact functional equivalence.",

  result:
    "Reduced the optimized software implementation from 259 to 82 assembly instructions, a 68% reduction, while achieving approximately 6× lower cycle count than the baseline implementation. The ASIC design achieved a 15-stage pipelined architecture at approximately 5,280 gate equivalents and produced a bit-exact match with the software reference during RTL simulation.",
};